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HANBit
HMN1288DV
Non-Volatile SRAM Module 1Mbit (128K x 8-Bit), 32Pin-DIP, 3.3V Part No. HMN1288DV
GENERAL DESCRIPTION
The HMN1288DV Nonvolatile SRAM is a 1,048,576-bit static RAM organized as 131,072 bytes by 8 bits. The HMN1288DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry, which constantly monitors the single 3.3V, supply for an outof-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after V CC returns valid. The HMN1288DV uses extremely low standby current CMOS SRAM 's, coupled with small lithium coin cells to provide non-volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 70, 85, 120, 150 ns w High-density design : 1Mbit Design w Battery internally isolated until power is applied w Industry-standard 32-pin 128K x 8 pinout w Unlimited write cycles w Data retention in the absence of V CC w 10-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss w Conventional SRAM operation; unlimited write cycles NC
PIN ASSIGNMENT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 NC /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3
A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
OPTIONS
w Timing 70 ns 85 ns 120 ns 150 ns
MARKING
- 70 - 85 -120 -150
32-pin Encapsulated Package
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HMN1288DV
FUNCTIONAL DESCRIPTION
The HMN1288DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A 0-A16) defines which of the 131,072 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN1288DV operates as a standard CMOS SRAM. During power -down and power-up cycles, the HMN1288DV acts as a nonvolatile memory, automatically protectin g and preserving the memory contents. The HMN1288DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in t ODW from its falling edge. The HMN1288DV provides full functional capability for Vcc greater than 3.0V and write protects by 2.8 V nominal. Powerdown/power-up control circuitry constantly monitors the V CC supply for a power-fail-detect threshold VPFD. When VCC falls below the V PFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become "don't care" and all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts.
BLOCK DIAGRAM
A0-A16 DQ0-DQ7
PIN DESCRIPTION
A0-A16 : Address Input /CE : Chip Enable Vss : Ground
/OE /WE
128K x 8 SRAM Block
Power
/CE CON
DQ0-DQ7 : Data In / Data Out
/CE
Power - Fail Control Lithium Cell
VCC
/WE : Write Enable /OE : Output Enable VCC : Power (+3.3V) NC : No Connection
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HMN1288DV
TRUTH TABLE
MODE Not selected Output disable Read Write /OE X H L X /CE H L L L /WE X H H L I/O OPERATION High Z High Z DOUT DIN POWER Standby Active Active Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER DC voltage applied on V CC relative to V SS DC Voltage applied on any pin excluding V CC relative to VSS Operating temperature Storage temperature Soldering temperature SYMBOL VCC VT TOPR TSTG TSOLDER RATING -0.5V to Vcc+0.5 -0.3V to 4.6V 0 to 70C -65C to 150C 260C For 10 second VT VCC+0.3 CONDITIONS
NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Condit ions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR )
PARAMETER Supply Voltage Ground Input high voltage Input low voltage SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.3 TYPICAL 5.0V 0 MAX 5.5V 0 Vcc+0.3V 0.8V
NOTE: Typical values indicate operation at TA = 25
CAPACITANCE (TA=25 , f=1MHz, VCC=5.0V)
DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage = 0V Output voltage = 0V SYMBOL CIN CI/O MAX 10 10 MIN UNIT pF pF
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DC ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin VCC VCCmax )
PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output low voltage CONDITIONS VIN=VSS to VCC /CE=VIH or /OE=VIH or /WE=VIL IOH=-1.0mA IOL= 2.0mA Threshold Power-fail Deselect Voltage Voltage (THS = VSS ) Standby supply current /CE=2.2v /CE VCC-0.2V, Standby supply current 0V VIN 0.2V, or VIN VCC-0.2V Operating current Supply switch-over voltage Power supply /CE=VIL, II/O=0 , VIN = VIL or V IH, Read ICC VSO 2.5 12 V ISB1 30 A ISB 0.6 Select VPFD 2.8 2.9 3.0 V SYMBOL ILI ILO VOH VOL MIN 2.4 TYP. MAX 3.0 3.0 0.4 UNIT A A V V
NOTE: Typical values indicate operation at TA = 25 .
CHARACTERISTICS (Test Conditions)
PARAMETER Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) VALUE 0 to 3V 5 ns 1.5V ( unless otherwise specified) See Figures 1and 2
+5V DOUT 1K
Figure 1. Output Load A
+5V DOUT 1.9K 5
1.9K
100
1K
Figure 2. Output Load B
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READ CYCLE (TA= TOPR, VCCmin VCC VCCmax )
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable to Output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output high Z Output hold from address change SYMBOL tRC tACC tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A CONDITIONS MIN 70 5 5 0 0 10 -70 MAX 70 70 35 25 25 MIN 85 5 0 0 0 10 -85 MAX 85 85 45 35 25 -120 MIN 120 5 0 0 0 10
HMN1288DV
-150 MIN 150 10 5 0 0 10 MAX 150 150 70 60 50 -
UNIT ns ns ns ns ns ns ns ns ns
MAX 120 120 60 45 35 -
WRITE CYCLE (TA= TOPR, Vccmin Vcc Vccmax )
PARAMETER Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write SYMBOL tWC tCW tAS tAW tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Note 4 Note 4 Note 5 Note 5 Note 1 Note 2 Note 1 Note 1 Note 3 Note 3 CONDITIONS MIN 70 65 0 65 55 5 15 30 0 10 0 5 -70 MAX 25 MIN 85 75 0 75 65 5 15 35 0 10 0 0 -85 MAX 30 -120 MIN 120 100 0 100 85 5 15 45 0 10 0 0 MAX 40 -150 Min 150 100 0 90 90 5 15 50 0 0 0 5 Max 50 UNI T ns ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the over lap of allow /CE and a low /WE. A write begins at the later transition of /CE going low and /WE going low. 3. Either t WR1 or tWR2 must be met. 4. Either t DH1 or tDH2 must be met. 5. If /CE goes low simultaneously w ith /WE going low or after /WE going low, the outputs remain in high impedance state.
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HMN1288DV
POWER-DOWN/POWER-UP CYCLE
PARAMETER VPFD(max) to VPFD(min) VCC Fail Time VPFD(max) to VSS VCC Fail Time VPFD(max) to VPFD(min) VCC Rise Time SYMBOL tF tFB tR Delay after Vcc slews down Write Protect Time tWPT past VPFD before SRAM is Write-protected. Chip Enable Recovery VSS to VPFD (min) VCC Rise Time tCER tRB 40 1 120 ms s 40 250 s CONDITIONS MIN 300 150 10 TYP. MAX UNIT s s s
TIMING WAVEFORM - READ CYCLE NO.1 (Address Access)*
1,2
tRC Address tACC tOH DOUT Previous Data Valid Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
CE tACE tCLZ DOUT High-Z tRC
tCHZ
High-Z
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*1,5
HMN1288DV
- READ CYCLE NO.3 (/OE Access)
tRC Address tACC /OE tOE DOUT tOLZ High-Z tOHZ Data Valid High-Z
NOTES:
1. /WE is held high for a read cycle. 2. Device is continuously sele cted: /CE = /OE =V IL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = V IL. 5. Device is continuously selected: /CE = V IL
- WRITE
CYCLE NO.1 (/WE-CONTROLLED)
*1,2,3
tWC Address tAW tCW /CE tAS /WE tDW DIN tWZ DOUT Data Undefined (1) Data-in Valid tOW High-Z tDH1 tWP tWR1
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- WRITE CYCLE NO.2 (/CE-Controlled)
*1,2,3,4,5
HMN1288DV
tWC Address tAS /CE tWP /WE tDW DIN tWZ DOUT Data Undefined High-Z Data-in tDH2 tAW tCW tWR2
NOTE:
1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either t WR1 or tWR2 must be met. 5. Either t DH1 or tDH2 must be met.
- POWER-DOWN/POWER-UP
TIMING
tPF VCC 4.75 VPFD VPFD 4.25 VSO tFS tWPT /CE tDR VSO tPU tCER
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HMN1288DV
PACKAGE DIMENSION
Dimension A B C D E F G H I J Min 1.680 0.720 0.365 0.015 0.008 0.590 0.015 0.090 0.080 0.120 Max 1.680 0.740 0.375 0.025 0.013 0.630 0.021 0.110 0.110 0.160
J A I B C D E H G
All dimensions are in inches.
F
ORDERING INFORMATION
H M N 1288 D V - 70 I
Operating Temp. : Blank = Commercial (0 to 70 C ) I = Industrial (-40 to 85C) Speed options : 70 = 70 ns , 85 = 85 ns 120 = 120 ns, 150 = 150 ns Operating Voltage : 3.3V
Dip type package
Device : 128K x 8 bit Nonvolatile SRAM HANBit Memory Module
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